Computer Engineering Ph.D. Candidate Tackles VLSI Layout Design Automation

Dec 7, 2017

CSE Ph.D. candidate Ilgweon Kang is preparing for the final defense of his doctoral dissertation, which is scheduled for Tuesday, Dec. 12 at 10am in CSE room 3109. His dissertation on "Floorplan Representation, Global Placement and Routability Analysis for VLSI Layout Design Automation" is in fulfillment of the Ph.D. degree in Computer Science (Computer Engineering).

CSE Ph.D. candidate Ilgweon Kang

Kang's advisor, CSE professor C.K. Cheng, will chair the faculty panel, which includes CSE professors Ron Graham and Andrew Kahng, and ECE professors Bill Lin and Farinaz Koushanfar. The final defense examination is open to the public.

According to Kang's abstract, "designing ICs has become much more sophisticated and complicated... [and] IC layout design has direct impacts on timing closure, die utilization, routability, and design turnaround time (TAT); these in turn affect the classic design metrics of operating frequency, yield, power consumption and cost."  As a result, argues Kang, physical-design engineers face many nontrivial challenges, and design costs increase rapidly as industry looks for higher efficiency on design optimization, automation, and innovation for better performance and cost reduction.

In his dissertation, Kang focuses on new design methodologies for improved IC layout development and design automation.  He introduces new 3D floorplan representations, which enhance 3D IC physical-design automation.  "Our floorplan representations are potentially extendable toward multiple dimensions by adding factors such as time, energy, temperature, security, etc.," he notes. Kang also describes a constraint-driven and routability-driven global placement engine called RePlAce -- a "flat, nonlinear analytical global placement engine with electrostatics-based global-smooth density cost function." RePlAce also addresses routing congestion. 

In addition, Kang presents a new framework for rapid identification of the design rule-correct routability through well-organized Boolean satisfiability (SAT) formulation.  "Our routability analysis method is developed on the foundation of multi-commodity flow theory and SAT-friendly, integer linear programming (ILP)-based detailed routing formulation.