CSE242A - Integrated Circuit Layout Automation



Couplings among timing, circuits and spatial embedding in nanometer-scale CMOS design. The role, and key problems, of physical layout in IC implementation. Example topics: RTL-to-GDSII methodologies, analyses and estimations, partitioning, floor planning, placement, routing, special net routing, cell generation, compaction.


CSE 241A or consent of instructor

New Fall 2002