ASPLOS Best Paper Win for Technique to Improve Computer Processing

May 21, 2024
Computer Science Professor Dean Tullsen

University of California San Diego professor Dean Tullsen and alumnus Sankara Prasad Ramesh (MS ’23) of the Jacobs School of Engineering Department of Computer Science and Engineering are working to untangle a complex bottleneck impacting modern high-performance processors.

They are part of a team that includes researchers from Princeton University and Intel that has proposed a novel instruction prefetching technique to target instruction cache misses and improve processing performance. Their paper, “PDIP: Priority Directed Instruction Prefetching,” received one of six best paper awards recently at the 2024 ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS).

Prior work to address front-end bottlenecks focused on increasing the cache size or utilizing fetch directed instruction prefetching (FDIP). The team’s work augments FDIP, and overcomes its limitations with larger instruction footprints, by pairing priority directed instruction prefetching (PDIP) with an instruction cache, both carefully designed to work with a decoupled front-end.

ASPLOS is the premier academic forum for multidisciplinary computer systems research spanning hardware, software, and their interaction.

In addition to Tullsen and Ramesh, other coauthors include Bhargav Reddy Godala and David I. August with Princeton University; Jarad Stark, Andre Seznec, and Gilles A. Pokam, of Intel.

This material is based upon work supported by Intel, and the National Science Foundation under Grant CCF-2107257.

--Kimberley Clementi